Schematics and PCB Layout

The PLT Demo Board (v2) is OSHWA-certified, with design files published at https://github.com/bcdevices/plt-docs / PLT-DEMOv2, under the CERN Open Hardware Licence Version 2 - Strongly Reciprocal.

Test Points

PLT Demo Board (v2) Test Points

Test point	Net name	Label	Description
TP1	VBUS	VCC IN	USB Power
TP2	(unnamed)	BAT-CHG	Charge Status
TP3	BAT_CHGB	BAT_CHG	Charge Status
TP4	BAT_SENSE	BAT-SENSE	Battery voltage sense
TP5	(unnamed)	5V	Voltage Regulator Output
TP6	GND	GND	Ground
TP7	GND	GND	Ground
TP8	GND	GND	Ground
TP9	DCDC	DCDC	nRF52 DC Decoupling
TP10	VDD	VDD	nRF52 Power
TP11	SWDIO	SWDIO	nRF52 SWD
TP12	NRST	NRST	nRF52 SWD
TP13	SWDCLK	SWDCLK	nRF52 SWD
TP14	GND	GND	Ground
TP15	+5VOUT	+5V Input	5V Input
TP16	+3V3OUT	+3V3 Input	3.3V Input
TP17	UART_RTS	UART-RST	nRF52 UART RTS
TP18	UART_TXD	UART-TXD	nRF52 UART TxD
TP19	UART_CTS	UART-CTS	nRF52 UART CTS
TP20	UART_RXD	UART-RXD	nRF52 UART RxD
TP21	VR	VR	Variable Resistor
TP22	SWO	SWO	nRF52 SWD
TP23	I2C_SCL	SCL	nRF52 I2C
TP24	I2C_SDA	SDA	nRF52 I2C
TP25	+24V	+24V Input	24V Input
TP26	(unnamed)	Divider 10V	Divider 10V
TP27	(unnamed)	Divider 5V	Divider 5V
TP28	+1V8OUT	+1V8 Input	1.8V Input
TP29	AGND1	AGND1	R58: 4.7kΩ
TP30	AGND2	AGND2	R59: 4.7kΩ
TP31	AGND3	AGND3	R60: 4.7kΩ
TP32	AGND4	AGND4	R60: 4.7kΩ
TP33	(unnamed)	10uF CAP	C42: 10μF
TP34	(unnamed)	10uF CAP	C42: 10μF
TP35	(unnamed)	100nF CAP	C43: 100nF
TP36	(unnamed)	100nF CAP	C43: 100nF
TP37	(unnamed)	100pF CAP	C44: 100pF
TP38	(unnamed)	100pF CAP	C44: 100pF

External References

• OSHWA UID US002054: BLUE CLOVER PLT DEMO BOARD, VERSION 2

• Open Source Hardware Association (OSHWA)

• CERN Open Hardware Licence Version 2 - Strongly Reciprocal | Software Package Data Exchange (SPDX)

See also

• bcdevices/plt-docs/PLT-DEMOv2: Design files for the PLT Demo Board (v2)