Schematics and PCB Layout

The PLT Demo Board (v2) is OSHWA-certified, with design files published at https://github.com/bcdevices/plt-docs / PLT-DEMOv2, under the CERN Open Hardware Licence Version 2 - Strongly Reciprocal.

Test Points

PLT Demo Board Test Points

TP

Signal

Description

TP1

VBUS

USB Power

TP2

CSO

Charge Status Output

TP3

GND

Ground

TP3

BATT_CHGB

Battery charge detection

TP4

BAT_SENSE

Battery voltage sense

TP5

5V

Voltage Regulator Output

TP6

GND

Ground

TP7

GND

Ground

TP8

GND

Ground

TP9

DCDC

nRF52 DC Decoupling

TP10

VDD

nRF52 Power

TP11

SWDIO

nRF52 SWD

TP12

NRST

nRF52 SWD

TP13

SWDCLK

nRF52 SWD

TP14

GND

Ground

TP15

+5VOUT

5V Input

TP16

+3V3OUT

3.3V Input

TP17

UART_RTS

nRF52 UART

TP18

UART_TXD

nRF52 UART

TP19

UART_CTS

nRF52 UART

TP20

UART_RXD

nRF52 UART

TP21

VR

Variable Resistor

TP22

SWO

nRF52 SWD

TP23

I2C_SCL

nRF52 I2C

TP24

I2C_SDA

nRF52 I2C

TP25

+24V

24V Input

TP26

Divider 10V

TP27

Divider 5V

TP28

+1V8OUT

1.8V Input

TP29

AGND1

R58: 4.7kΩ

TP30

AGND2

R59: 4.7kΩ

TP31

AGND3

R60: 4.7kΩ

TP32

AGND4

R60: 4.7kΩ

TP33

C42: 10μF

TP34

C42: 10μF

TP35

C43: 100nF

TP36

C43: 100nF

TP37

C44: 100pF

TP38

C44: 100pF

External References